Tim Michels
F5 Distinguished Engineer and Architect integrating concepts for platform design, hardware acceleration (custom and COTS), software stack functional delineation and abstraction, to create hyper-converged appliances, chassis, and COTS systems.
Appears in 2 Episodes
KV cache is the real inference bottleneck (Not GPUs)
GPUs get all the attention, but in inference, the real bottleneck is often memory, specifically the KV cache. In this episode of Pop Goes the Stack, Lori MacVittie sit...
The DPU Awakening: Silicon Muscle for AI Mayhem
This week on Pop Goes the Stack, we crack open the next frontier of enterprise infrastructure: DPUs (Data Processing Units). AI factories aren’t just stressing your ne...